Constraint Generation and Verification
SDC Promotion
SDC Demotion and Budgeting Toolbox
Exceptions Toolbox
Multi-mode & Hierarchical SDC Management
SDC Equivalency
Signal integrity enablement
Automatic clock & mode discovery
clock tree analysis
Intuitive clocking visualization


TEC – Timing Equivalence Checking
July 01, 2021


Address the challenges of RTL
June 01, 2021


Flawed Constraints Survey…
June 6, 2016

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News and Events
Excellicon Introduces ConStruct; An RTL Floorplanning, Partitioning Explorer and Floorplan Verification Platform
Dec 1, 2021
Excellicon products included in Samsung Advanced Foundry Ecosystem; SAFE™
Nov 15, 2021

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Customer Feedback

Excellicon’s comprehensive tool set is the necessary infrastructure to formalize and automate the constraints development flows. …Read More
Hideyuki Okabe

Senior Manager Digital Design Technology Department
Renesas System Design Co., Ltd.
LG Electronics
Excellicon provides a comprehensive foundation for us to address the efficiency of our constraints development process through all stages of design. …Read More
Dr. Woohyun Paik

Senior vice president, SIC Center
LG Electronics
We reduce the work in clock analysis significantly by Excellicon’s smart clock tree analyzer which gives us simple view of IP structure. …Read More
Akihiro Yoshitake

General Manager of SoC Design Division
Socionext Inc.
Excellicon’s solution enabled us to achieve a faster and more accurate path to timing closure. …Read More
Dr. Paolo Miliozzi

Senior Director of SOC Technology and Physical Design
Minimizing timing-related iterations allows our customers to enjoy the benefits of fast turnaround time and reduced cost
Jonathan Park

Baysand Inc.

ConMan differed from traditional tools by providing a complete constraints solution.…Read More



Constraints Generation

Automatically generate SDC’s for any mode, for any layer of hierarchy and for any application such as Synthesis, P&R, STA, CDC, or Power Analysis. Generate flat, hierarchical or merge-mode SDC’s.
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Constraints Management

Manage multi-mode timing constraints in the same database, for RTL & Gates, any layer of hierarchy and for different phases of the design cycle. Seamless interface to MS Excel also supported. Learn More

SDC Promotion

Promote IP SDC constraints from lower level of hierarchy to any upper level of the hierarchy. Multiple methods supported to customize SDC promotion that helps shorten development time by months. Learn More

Constraints Verification

Lint and Verify the timing constraints with zero noise, and sign-off with confidence. Incrementally generate corrected constraints or automatically convert the original SDC, Signal Integrity compliant. Learn More

Exceptions Toolbox

Use formal & proprietary technology to validate “Structural” as well as “Timing-Intent” type of exceptions such as False and Multi-Cycle paths. Generate System Verilog Assertions for independent verification. Learn More

SDC Demotion & Budgeting Toolbox

Demote SDC’s to any lower level hierarchy. Use Budgeting Platform to generate IO delays based on multiple budgeting options. Analyze & Verify budgets or redistribute them automatically. Learn More

Equivalency Checking

Validate if the block level timing constraints are in-context equivalent to the top level timing constraints. Or whether the top level timing constraints for RTL and Gates have the same timing intent. Learn More

Clock Visualization & Analysis

Understand clocking structure by generating an intuitive clocking diagram. Perform “what-if” analysis to understand the clock propagation behavior or to debug the clock network logic. Visualize the timing waveforms and clock relationships. Learn More

Design Analysis

Perform Clock tree, Macro partitioning or Bad paths analysis at different stages of the design cycle. Take corrective actions early-on in order to prevent surprises during the late stages of the Tapeout cycle. Learn More

Tools Usage

Where our tools fit in the ASIC/FPGA flow. Learn More

Excellicon Profile

Excellicon provides Electronic Design Automation (EDA) software tools targeted at solving complex problems associated with timing closure and functionality of SoC designs. Excellicon software enables designers to increase productivity, use a systematic and correct-by-construction approach resulting in reduction in chip development cycle by orders of magnitude. LEARN MORE
Excellicon products are targeted at solving the complexity and issues faced by designers from RTL design all the way through to the final timing closure stage where implementation expertise is in need of design knowledge.
We are present in 6 countries around the world