Constraints Certifier Platform
ConCert is a sign-off platform providing a unique system for verification, demotion and budgeting of timing constraints at any stage of the ASIC or FPGA flow.
The ConCert platform contains the following components:
- Constraints Verification
- Exceptions Toolbox
- Demotion and Budgeting Toolbox
- Equivalence Checking
- Design Analysis
ConCert uses formal algorithms to verify the timing constraints thus providing accurate in-depth analysis of both the design and its associated timing constraints.
ConCert’s approach to constraints verification is different than the traditional tools available in the market today.
Traditional tools are primarily SDC linters focusing on syntax and basic correctness through the use of thousands of rules. This invariably produces a lot of noise in the output reports. Furthermore the timing intent is lost and cannot be analyzed by such traditional tools.
ConCert in addition to linting, also makes use of its formal engine to analyze the behavior of the design and the SDC file. The timing intent of the design and the associated SDC file is extracted and compared to produce precise analysis reports. This method leads to elimination of noisy outputs and expands the constraints verification arena into the next generation, well beyond syntax and basic checks
In addition, through ConCert, designers can also generate incremental SDC in case the original SDC had missing constraints, or to make the SDC Signal Integrity compliant.
Timing Constraints files often contain a great deal of exceptions such as False paths (FP’s) and Multi-cycle paths (MCP’s). Such Exceptions are typically categorized into “Structural” and “Timing Intent” Exceptions. The Structural exceptions are dependent on the design structure and can be verified through formal techniques. However the Timing intent type of exceptions are independent of the design structure i.e., they are based on designers intent (say setting of the false path constraint to all reset pins), thus formal techniques cannot be used to verify them.
Roughly 20% of FP & MCP exceptions in a typical timing constraints file are of the structural type. The challenge however lies in the remaining 80% of exceptions which are of the timing intent nature as defined by the RTL designer at the time of functional design. Since, formal techniques cannot be used for such type of exceptions, designers traditionally validate them through manual review of constraints files.
ConCert-ET, an add-on to ConCert is the only tool available in the market today that provides a comprehensive platform to validate not only the Structural exceptions through formal means, but also the Timing Intent types of exceptions using proprietary methods.
Typically, the RTL is simulated to ensure functional correctness. The timing associated with the design is captured in SDC format independent of the RTL functionality. The two aspects of the design, i.e., the functionality and the timing only align much later in the design cycle when SDF annotated GLS is performed.
Even with the availability of static tools such as Constraints verification tools, LEC, STA, CDC Analysis, and Glitch analysis tools, one would assume that there is no need for GLS. However, today no EDA solution exists that can validate the timing-intent nature of the timing constraints. The timing-intent refers to the constraints that are independent of the design structure but are based on the designer’s intent. For example, complex clock waveforms defined in the SDC file; or false/multi-cycle paths specified in the SDC file that are not based on logic structure, rather are specified based on designer’s knowledge.
This necessitates the need for GLS to catch these kinds of issues. However, one major problem with GLS is that setting up the GLS environment is an extremely tedious task.
In order to circumvent these issues and to help simulate the design at an earlier phase of the ASIC cycle (without the need for delay annotation through SDF), Excellicon developed an ABSV (Assertion Based SDC Verification) feature where the relevant timing constraints are converted to SVA’s that can be used during simulation.
This method eliminates the need to run SDF annotated GLS, thereby reducing the cycle time significantly. The SVA’s can also be simulated at the RTL stage thus simplifying the overall flow altogether.
Demotion and Budgeting
ConCert-BT, an add-on to ConCert empowers the designers to perform constraints demotion and hierarchical budgeting with varying levels of accuracy spanning from RTL to physical domain.
The product has full capabilities for
- Constraints demotion
- Budget generation
- Percentage based
- Levels of logic based
- Delay based with intrinsic cell delays and layout parasitics
- Verification of budgets across all the macros
- Manual refinement of budgets
- Automatic redistribution of timing budgets based on STA timing slack values
- Hierarchical budget management with history of past budgets for each macro
Using ConMan, designers can promote the IP constraints to the top level and subsequently through ConCert-BT can demote the constraints to the macro level for P&R activity. ConCert-BT provides full flexibility in configuring the tool to either selectively demote some of the constraints or to automatically demote all the constraints.
Timing budgets also constantly change as design matures during the physical implementation. This includes RTL changes, to ECO’s, which may each result in imbalances of timing among various blocks in the design, that require adjustments in the IO delay values to address the timing violations between the macros. Designers have to find a way to redistribute the budgets to address the timing of failing paths; an exercise done manually which results in long iterations and often sub optimal timing for the chip.
With teams of physical implementation engineers working in parallel on their own blocks, the interface timing must account for accurate budgets in order for the top level timing to pass without any violation.
Front-end designers can use ConCert-BT to generate the appropriate budgets at the early phase of the implementation cycle using percentage based or levels of logic based budgeting, while the back-end engineers can take advantage of the most powerful physical budgeting which derives the budgets using floorplan information and manages the budgets throughout the timing closure cycle including the creation of timing models, leading to final iterations before tape-out.
ConCert-BT offers a comprehensive solution of not only validating the correctness of existing budgets across the macros, but also displays the budgets through its intuitive BudgetMap GUI. Through BudgetMap, designers can easily debug the failing paths and take corrective actions.
Invariably constraints change as the design progresses from one design phase to the other. New constraints may get added or existing constraints modified which may cause the timing constraints to be inequivalent and lose the original intent.
Since, SoC’s are assembled hierarchically, there may be a case where the block level timing may not be in-context to the top level timing. This could be problematic when top level full flat STA is performed.
Thus, there is a need to prove timing equivalency between the constraints. ConCert provides two types of equivalency methods:
- Top to Top – To check for constraints equivalency between different phases of design cycle
- Top to Block – To check for in-context nature of block level constraints w.r.t. the top level