A Visual and Interactive tool for Pre-CTS Analysis and Post-CTS Verification

ConTree is a clocking logic visualization, analysis and verification tool. It is used for both pre-CTS clocking analysis as well as post-CTS clock tree verification.

ConTree is intended to help RTL and Implementation engineers with the clock design in order to minimize debugging effort and to understand the clock network and topology. Implementation engineers can use this product to define the CTS timing constraints and to eliminate unnecessary CTS iterations.

    Clock Tree Analysis

    Prior to running automated CTS tools, ConTree can be used to analyze the clocking architecture and to generate a detailed visual diagram of the clock logic, including the clock topology and the associated waveforms, in order to understand the clock propagation across the SOC. User can automatically visualize the entire clock network, with flexibility to interactively manage logical and physical hierarchies, combinational logic etc., in order to simplify the clocking diagram for easy readability and documentation. ConTree can also be used to detect intended or unintended changes in the clock network often encountered during the RTL evolution.

    Clock propagation with case values and clock sense. Combinational cells collapsed as logic cloud.

    ConTree enables designers to explore the clocking logic for downstream interactions that is useful in determining the clock interactions, clock tree exceptions, skew groups, mode conflicts and other such information. This information is the basis of the CTS spec file which is used as the seed input to the CTS engine of the P&R tool and is needed for optimized clock tree with better clock latency and skew along with overall timing.

    Skew Groups Analysis with cross-probing to the schematic

    Clock Tree Verification

    For post-CTS, ConTree is used to validate the structure of the clock tree early on (instead of finding issues during late stages of STA) in order to reduce the number of CTS iterations.

    Clock Tree verification with cross-probing to the schematic

    The CTS verification uses formal and other technologies using the netlist, DEF, UPF and the SDC as input.

    In this mode, the tool provides capabilities to check the CTS implementation across power domains, balancing issues, DRC’s, clock tree exceptions, mode conflicts, and validation of any SDC associated with CTS.