RTL Floorplanner, Partitioning, and Floorplan Verification
ConStruct is an early RTL Floorplanner, partition explorer, and floorplan verification tool. It can further be used to generate the partitioned RTL based on specified criteria.
ConStruct works seamlessly with Excellicon’s other tools in order to provide a full platform of implementation solution.
Initial phases of the chip design involves huge amount of planning where designers try to estimate the area, data flow, clock topology etc., in order to determine the ideal partitioning candidates for hardening which is needed for optimal floorplan that meets the PPA targets. This is followed by a preliminary floorplan which is refined multiple times as more accurate information becomes available as the chip undergoes the rest of the implementation process.
However, RTL development, partitioning decisions and floorplanning is often done independent of each other, which often leads to highly suboptimal results. Consequently, multiple expensive iterations are needed in order to meet the target PPA.
ConStruct streamlines the whole process by enabling the RTL or Implementation engineers, early access to all the information needed to rapidly derive (manually or automatically) optimal partitions and the floorplan. This is achieved by performing RTL analysis, exploring the area, timing, connectivity, data-flow and other factors.
Furthermore, ConStruct also adds the capability to validate the existing floorplan against the RTL (as well as other factors) so that the floorplanning or RTL issues can be identified at an early stage.
- RTL Analysis, Exploration and Partitioning
- Area and Timing
- Connectivity Analysis
- Clock and Data Topology
- Feedthrough Paths
- Glue Logic
- Early RTL Floorplanning
- Automatic floorplan based on chosen criteria
- Manual Floorplanning
- Padring Designer
- Floorplan Verification
- Validate existing floorplan for correctness
- Supports both Abutted and Channel based designs
RTL Analysis, Exploration & Partitioning
ConStruct is designed to provide designers the capability to explore the RTL and suggest various partitioning options based on the chosen criteria. Optionally, ConStruct can be used to repartition the RTL along with the SDC.
ConStruct performs automatic or manual floorplanning. In the automatic mode, the tool evaluates multiple floorplan scenarios and chooses the optimal solution based on the specified criteria such as critical timing paths, area or other parameters. The tool supports hierarchical floorplanning and incorporates a synthesis and timing engine.
RTL design without considering the physical ramifications and vice-versa, generally lead to expensive iterations where either the RTL or the floorplan needs to be modified. ConStruct is the only tool in the industry that adds the floorplan verification at an early stage. Exhaustive set of rules check for inconsistencies between the RTL, Floorplan, Port placement and Routing etc.