Excellicon provides a comprehensive foundation for us to address the efficiency of our constraints development process through all stages of design. Excellicon’s tools enable us to address the gaps in constraints development and build a path to final timing closure.
Dr. Woohyun Paik
Senior vice president, SIC Center
LG Electronics
Korea

Understanding clock structures adequately and cleaning timing constraints on early design stage is one of key tasks in successful SoC implementation, especially when the SoC is integrated with dozens of IP macros. We reduce the work in clock analysis significantly by Excellicon’s smart clock tree analyzer which gives us simple view of IP structure. We could build timing constraints of those IPs and promote them to SoC level much quicker
Akihiro Yoshitake
General Manager of SoC Design Division
Socionext Inc.
Japan

Excellicon’s solution enabled us to achieve a faster and more accurate path to timing closure. We tried other tools available on the market, but Excellicon’s products are the ones which allowed us to enhance our methodology to address constraints issues related to timing closure of our SOC’s and helped us to eliminate unnecessary iterations due to incomplete constraints.
Dr. Paolo Miliozzi
Senior Director of SOC Technology and Physical Design
Maxlinear
U.S.A.

Minimizing timing-related iterations allows our customers to enjoy the benefits of fast turnaround time and reduced cost
Jonathan Park
EVP & CTO
Baysand Inc
U.S.A.

ConMan differed from traditional tools like Fishtail Focus, Atrenta
Spyglass-Constraints, Blue Pearl, Synopsys GCA and Cadence’s stuff by
providing a complete constraints solution. In addition, none of these tools
solve the real-world issues like timing problem from bad IO constraints, or
providing a mechanism to define the clock to clock relationships like MCP’s
and FP’s in a meaningful manner, ConMan does. …Read More