News and Events
Excellicon’s ConCert-Synergy provides a comprehensive approach to validation of constraints beyond traditional equivalency checks
June 19, 2018 – Laguna Hills, CA
Excellicon Inc. an innovative provider of end-to-end timing constraints products announced release of one of its latest product “EQ-InSync” for automated validation of timing constraints through all stages of design for equivalency. of structural as well as timing intent class of false and multi-cycle paths. The users of Excellicon products can now very simply and automatically validate their existing timing exceptions comprehensively.
The changes in the design are plentiful and continuous through the entire ASIC process. The need for generation of derivative designs, cloning parts of chip or IP, as well as logical restructuring of the design require continuous monitoring of all aspects of design specially with respect to timing constraints which are traditionally developed manually with much human intervention. Additionally IP repositories shall have a method of ensuring that the constraints are Equivalent and InSync with the design at all layers of hierarchy. Generally the SDC applied to RTL is going to go changes as design gets to optimization and ECO stage. Often the intent behind the timing constraints is lost evaluating the risk of chip failure.
EQ-InSync is offered as part of the ConCert toolset offering. User will be able to conveniently load pre and post optimized designs along with their respective SDC’s. The tool takes care of verification and validation of resulting SDC for correctness. Any changes introduced as SDC evolves from initial design stages to tapeout will be flagged for fixes.
“Eq-InSyn is unique from what traditionally have been introduced as equivalency checking. As the design is validated through and with respect to all layers of hierarchy it is crucial for an automated solution to be able to validate the correctness of timing constraints as it was intended when design started” said Himanshu Bhatnagar, CEO of Excellicon. “We believe with our latest offering of can plug yet another gap in validation very critical aspect of timing constraints design to ensure actual end-to-end timing solution.
Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products Constraints Manager, Constraints CerTifier, Exception-ToolBox (ET), Budgeting-Tool Box (BT), Equivalence-Checker (EQ), and ConTree address the needs of designers at every stage of SOC design and implementation in a unified environment. – Timing Closure; Done Once! Done Right!
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