News and Events
Excellicon deepens the End-to-End Timing Constraints solution by expanding the leading product capabilities
Laguna Hills, CA – June 13, 2018
Excellicon Inc. an innovative and number one provider of end-to-end timing constraints analysis and verification products announced that is expanding the capabilities of its already comprehensive products to address the timing constraints development and verification from early stages of design development at RTLeval to final GDS.
Excellicon products go beyond a set of feature lists. Although the features such as SDC generation, verification, promotion, demotion, budgeting, equivalence checking, merging of modes, Liberty file generation, hierarchical constraints generation & management, etc. are important part of the products, the products are designed not only to work as stand alone (task oriented) type of validation but also as a comprehensive suite of tools to address all aspects of the timing constraints design. For majority of users the real impact and power of the tool comes when integrated onto design flow and as part of design the methodology. Users can customize and setup their methodology using the products to quantify the timing constraints quality of deliverables.
Designers involved in chip design methodology, often face an information gap between RTL and gates. As design progresses from conceptual RTL design to implementation at the gate level the discontinuity of the timing information is often the biggest culprit for wasteful iterations. Interestingly this information is mostly available during the simulation, yet it is not used at implementation level unless there is a timing closure issue. Such timing issues trigger long iterations back to the RTL design stage trying to gain guidance to the behavior of the overall design.
“A measureable end-to-end timing closure methodology is what provides the most value and efficient use of a tool feature list. We see many products touting their feature list while pay little to no attention to the “HOW” aspect of such features into the design flow where the impact is greatest. While providing a rich set of features is essential, Excellicon can enable design teams to implement methodologies to quantify and measure constraints development process. Excellicon inherent tool architecture allows design teams to customize design methodology, while enabling individual designers to take advantage of rich and comprehensive tool feature while being able to explore the design as part of their work”
Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products Constraints Manager, Constraints CerTifier, Exception-ToolBox (ET), Budgeting-Tool Box (BT), Equivalence-Checker (EQ), and ConTree address the needs of designers at every stage of SOC design and implementation in a unified environment. – Timing Closure; Done Once! Done Right!
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