News and Events
Excellicon Tools Used by Renesas to Streamline Timing Constraint Development Methodology
September 27, 2016
Excellicon Inc., an innovative provider of Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, validation, and Management, today announced Renesas, one of the top world leaders in providing semiconductor solutions, has licensed Excellicon Constraints tools. The tools are expected to speed delivery schedules in Renesas’ semiconductor development methodology.
Generation and validation of constraints is a challenge spread across the entire design flow, from front-end to back-end and final tape-out. Project managers are often challenged by the complexity of timing requirements for Today’s SOCs. The result is many iterations and delays in delivery schedules resulting from challenging timing specifications. Excellicon tools focus on reducing the challenge of multiple iterations between design and implementation teams resolving design timing closure issues. The tools address the challenges faced by designers regarding timing constraints (SDC) design and validation, which are often the cause for schedule delays. By using the Excellicon tools, Renesas can automate its timing constraints flow used for placement and routing of designs solutions as well as eliminate unnecessary design cycles in order to achieve higher levels of accuracy and efficiency in delivery schedules.
“Excellicon’s comprehensive toolset is the necessary infrastructure to formalize and automate the constraints development flows. We were able to demonstrate the value of the products in our flow and to use the tool capabilities to eliminate much of the manual effort. The Ecxellicon tools enable us to provide a formal and simplified automated approach for our design reviews.,” said Hideyuki Okabe, senior manager of Digital Design Technology Department at Renesas System Design Co., Ltd. “The tools further help us to avoid discontinuities in the timing constraint development flow while streamlining the path to final timing closure without having to invest in a costly iterative process.”
“Excellicon is excited to work with Renesas and strives to bring the designers a complete and automated constraints platform. Excellicon timing constraints synthesis and validation ensure completeness and correctness of timing constraints from the start to finish, avoiding multiple iterations,” said Rick Eram, VP of Sales and Marketing at Excellicon. “Our goal is to address the challenge in managing a patchwork of tools, internal scripts, and a great deal of manual effort by many design teams, while providing a verifiable, and repeatable timing constraints flow from RTL to Signoff, similar to toolsets available on functional flows. Recognition of our technology by a highly effective team at a world-renowned organization such as Renesas is an honor and validation of our missions.”
Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with necessary analysis and debugging infrastructures. Excellicon products ConMan, ConCert, ConDor and ExceptionsToolbox, address the Clock Analysis and timing Constraints needs of designers at every stage of SOC design and implementation in a unified environment. Timing Closure; Done Once! Done Right! www.excellicon.com
For more information contact:
Excellicon: Rick Eram