Automatic Constraints Compiler & Manager
ConMan is the first commercially available formal constraints compiler tool that automatically generates SDC for any level of hierarchy and for any mode of a SoC, thereby significantly shortening the timing closure cycle. ConMan provides an intuitive means of automatically compiling and managing sign-off quality correct-by-construction timing constraints for all applications.
ConMan also redefines the timing constraints landscape by aligning front-end to back-end early in the design cycle, thus eliminating the existing disconnect between timing assumed in simulation test benches, and the timing coded in the SDC files for implementation activities.
ConMan generates and maintains a single source of data for use by both front-end and back-end designers to capture, generate and manage design timing constraints for all modes of operation while providing feedback to designer at all stages of the design. Using ConMan designers can start generating timing constraints right from the start of RTL development by front-end engineers all the way to the implementation stage by back-end team. All information is traced through ConMan and can be reviewed through reports or visualization of simulated timing data.
Designer can manually feed timing information or optionally feed them from legacy SDC’s and/or through simulation results for any block of the design hierarchy. ConMan automatically verifies all input data using its powerful formal symbolic simulation engine and then assembles & propagates all timing data throughout the design hierarchy, resolves conflicts, and presents data to designer for further refinement, if needed.
The ConMan platform contains the following components:
- Multi-Mode Constraints Generation with only RTL or Gates as input
- Constraints Management
- Constraints Promotion
- Clock Visualization and Analysis
Multi-Mode Constraints Generation
ConMan generates comprehensive timing constraints in SDC format for any design hierarchy and for any mode. No knowledge of SDC syntax is required.
- SDCs for Any level of hierarchy, for Any mode & for Any Type – RTL and/or Gates
- Different types: Single Mode , Merged Mode – with choice of full flat or hierarchical
- 100% discovery of all Clocks and Mode pins
- Complete SDC with, Clocks, Timing Exceptions, Case Analysis, IO delays, Clock Groups, DRCs etc.
- Single Database for multi-mode, RTL & Gates timing constraints
ConMan provides a seamless interface to MS Excel, through which all timing constraints can be managed and/or modified external to the tool. This two way interface allows designers to use the familiar Excel Spreadsheets format to review the timing data and to modify it, if needed.
Most of the propagation of constraints today is done using manual methods of manipulating hierarchy delimiters. This technique increases the risk of error introduction and missed constraints during the editing process. Excellicon multi-propagation capabilities not only automates the process savings weeks of designer manual editing, but also provides a great deal of flexibility for designer to deal with any situation they may encounter as they attempt to generate proper top level constraints.
ConMan provides three techniques for promotion of lower level timing constraints to any layer of hierarchy. Mixing of all three methods is supported.
- Integration Method – Where the IP timing constraints are allowed change as a result of the top level design structure
- Isolation Method – Where the IP timing constraints are preserved as-is.
- In-Context Method – Where both top and lower level constraints are available but they are not in-context to each other. Promotion occurs with incremental propagation of timing constraints as defined and directed by designer.
Clock Visualization & Analysis
Understanding the clocking of any design is always one of the hardest tasks and very error prone. Existing solutions draw a complete schematic of the logic from which discerning the clocking logic is not only tough but sometimes impossible.
ConMan utilizes an intuitive abstract method of displaying the clocking diagram (automatically extracted from the HDL) from which designers can quickly understand the clocking logic for any level of hierarchy, full flat or hierarchical view. In addition, ConMan uses its formal engine to enable designers to perform clock propagation “what-if” analysis in order to create different modes of operation.