Excellicon Product Portfolio - ConMan

  • ConMan Description
  • Constraints Compilation
  • Automatic Mode Discovery
  • Hiearchical Propagation
  • Design and Timing Visualization
  • Propagate Timing Intent
  • Use Model
  • Target Applications
  • IP Visibility
  • FPGA Support
 

ConMan is the first commercially available formal constraints compiler tool that automatically generates SDC for any level of hierarchy and for any mode of a SoC, thereby significantly shortening the timing closure cycle. ConMan provides an intuitive means of automatically compiling, verifying and managing sign-off quality correct-by-construction timing constraints.

ConMan also redefines the timing constraints landscape by aligning front-end to back-end early in the design cycle, thus eliminating the existing disconnect between timing assumed in simulation test benches, and the timing coded in the SDC files for implementation activities.

ConMan generates and maintains a single source of data for use by both front-end and back-end designers to capture, generate, verify and manage design timing constraints for all modes of operation while providing feedback to designer at all stages of the design. Using ConMan designers can start generating timing constraints right from the start of RTL development by front-end engineers all the way to the implementation stage by back-end team. As more information becomes available, user can take advantage of available data to further refine and complete the constraints. All information is traced through ConMan and can be reviewed through reports or visualization of simulated timing data.

Designer can manually feed timing information or optionally feed them from legacy SDC's and/or through simulation results for any block of the design hierarchy. ConMan automatically verifies all input data using its powerful formal symbolic simulation engine and then assembles & propagates all timing data throughout the design hierarchy, resolves conflicts, and presents data to designer for further refinement, if needed.

ConMan is intended to be used from early stages of the ASIC design cycle to the final timing sign-off:

  • Preliminary RTL Integration stage (Lint clean, but not fully integrated design. May contain some blackbox components etc)
  • Integrated / Partially verified RTL (Design fully integrated with perhaps some block level verification)
  • Synthesis stage
  • Place and Route stage
  • STA signoff stage

Key feature highlights:

  • Generate formally correct and comprehensive timing constraints for any design hierarchy and for any mode
    • Fully flat, fully hierarchical or mixed – user choice
    •  
  • Automatic Mode Synthesis and Mode Interfusion (Automated Mode Propagation through hierarchy)
    • Eliminate the manual process of tracing the RTL/Gates to manually define the case_analysis points
    •  
  • Seamless, block level to top level SDC merging or top to block level splitting (Operates on the entire design as opposed to file by file model)
    • All timing constraints propagate up/down the design hierarchy in order to provide consistency across the full SoC
  •  
  • No prior knowledge of SDC syntax is required by designer
  •  
  • Only tool to capture the timing intent
    • Alignment of Simulation to the Synthesis/Implementation world – Right in the beginning
    •  
  • Automatic RTL to Gates Constraints mapping or Vice-Versa
    • ConMan eliminates the need to manually create multi-mode SDC files used for implementation and STA sign-off
  •  
  • Complete visibility inside 3rd party unknown IP
  •  
  • Full Tcl support
  •  
  • Support for Verilog, System Verilog and VHDL
  •  
  • GUI and Shell use model
 

ConMan generates comprehensive timing constraints in SDC format for any design hierarchy and for any mode. No knowledge of SDC syntax is required.

 
  • Fully flat, fully hierarchical or mixed – You choose
  • Automatic fixing and completion of timing constraints
  • Exception generation such as false and multi-cycle paths both for data as well as clocks
  • Generate any number of Merged Mode SDC's
  • Full support for creation and management of custom IP timings and reuse in other projects
  • Automatic RTL to Gates Constraints mapping in support of Multi-Mode flow – No need to create implementation related multi-mode SDC's
  • Context based SDC generation - block level SDC in the context of the design
  • Auto generation of environment files for CDC tools – Eliminate incorrect CDC analysis right from the start
  • Critical path & STA based constraints generation

 

Identifying and setting of modes for any SoC is always problematic. Designers have to unravel the mysteries of large combinational cloud and identify a single cell pin to set the appropriate case_analysis value.

ConMan is the only tool in the industry to provide a simple and unique method of, not only identifying the mode automatically but also associate the correct values for each defined mode. Based on our patented Colloqui algorithm ConMan uses symbolic formal analysis to extract and identify various modes in the design.

  • Automatic identification of Modes and Clocks
  • Automatic value assignment for each mode
  • Automatic identification and resolution of gating logic
  • Mode conflicts resolution across the hierarchy
  • Links seamlessly to the visualization and Compiler engines
  • Single click identifies the source of mode definition in either RTL or Gates or both

 

Using ConMan user can seamlessley navigate between various layers of hierarchy and the tool will automatically propagates necessary information in real time while checking for validity of data in the context of the entire design. ConMan allows users to design with the full knowldge of the design as opposed to being limited to file based propagation of information.

  • Propagate constraints from any layer of hierarchy to the entire design
  • Use existing SDC or VCD when available to extarct information to be shared for the entire design
  • Auto validation of any information entrerd by user for any layer of hierarchy for entire design

 

ConMan's patented methods provide a unique visualization experience to the users that not only are helpful for debugging purposes, but also are used for design reviews and for exchanging information between the design teams.

  • Built-in SDC Simulator simplifies the comprehension of overall timing pictures
  • Transparent, Mode and Clock Tree browser – Visualize the entire clocking structure in a simple yet descriptive manner
  • Complete visibility inside 3rd party unknown IP's
  • Intuitive and cross linked messaging System – All information are cross linked and cross probed
  • Coverage analysis per mode for full chip or any chosen block

 

ConMan is the industry's first EDA tool that seamlessly eliminates the disconnect between the front-end and back-end in terms of timing assumed in test benches used for RTL simulation versus the timing coded in the SDC file for backend implementation.

  • Links RTL simulation world to the backend implementation world seamlessly at any part of the design flow
  • ConMan assembles the information coming from multiple sources and propagates the timing throughout the design
  • Any discrepancy between the RTL structure and other sources is highlighted for resolution
  • Zero impact on simulation run-times

 

With today's design complexity, multiple modes and shrinking geometries, the numbers of SDC files are multiplying. ConMan provides an easy method to manage all timing data in one single database, while still allowing independence to the design teams that is inherently needed during any given project. ConMan also provides a mechanism for IP teams to manage the timing data in one single repository to be reused across the organization.

  • Single database encapsulating all constraints
  • Ease of handoff through incremental database
  • Simplicity in constraints management
  • Provides mechanism to generate timing constraints to support evolving design, until maturity and finally to sign-off stage
  • Seamless flow, that allows for design teams to work independently on their respective designs with final merging of their data at the full-chip level during integration.
  • Full support for creation and management of custom IP timings and reuse in other projects

 

Integration with tools in a typical design flow

  • Integrated solution for generation, validation, and management
  • Ease of use trough interface integration with Verdi for viewing of your design in familiar environment
  • Interface to ConCert product for one to one constrinats validation from ConMan environment
  • Ability to generate downstream tool setup files

 

  • Generate setup files for CDC analysis automatically and extend the usefulness of your existing tools
    • Accurate setup for CDC analysis from start - majority of the noise and CDC inaccuracies using standard tools is due to bad setup, automated setup eliminates the inaccuracies and empowers existing tools reduce the need for retooling
    • Enable true multi-mode CDC analysis
    • Enable CDC analysis for any layer of hiearchy with little effort
  • Enable more accurate vectorless power analysis
    • Perform vectorless power analysis as soon as RTL coding is ready even prior to generaiton of VCD
    • Power estimation using SDC and vectorless analsysis for any layer of hierarchy - user
  • Provide accurate SDC to your synthesis to avoid static generation of constraints by the synthesis engine
  • Simplify STA analysis by providing correct constraints from start

 

 

Gain complete understanding of any unknown IP

  • Discover the clocking structure of the design
  • Gain instant knowldge about the operation of the IP
  • Analyze the behavior of IP real time
  • Seamlessley integrate IP into design
  • Perform what-if analysis

 

 
  • Full FPGA constraints generation support
  • Common database for FPGA as well as ASIC development for seamless design migration
  • Understanding of FPGA structure