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Achieving Best Performance Timing Constraints Verification & Equivalency Checks for Extremely Large and Complex SOC Designs
Excellicon Inc. and MediaTek have concluded a joint effort to enable the fastest and most comprehensive fully automated Timing constraints verification and Equivalence Checking (TEC) solution in the industry, with performance which exceeds design team requirements and expectations for extremely large and complex SOC designs.
Timing constraints validation and timing closure has been an ever-growing challenge for ASIC designers for decades, and it is only becoming more challenging as design complexities and geometries are packing ever more devices onto a chip. Validating such complex constraints files as large as tens of gigabytes in size requires state of the art software which not only handles the complexity but also the sheer volume of data to be processed.
Verification of such constraint files require not only checking the syntax, accuracy or completeness of constraints files, but also other areas where productivity and comprehensiveness of validation work is at stake. For example, equivalence checking involves both tool performance as well as tool efficiency and effective use model in the design flow. Excellicon Concert; a complete timing constraints validation platform, and its TEC (Timing Equivalency Checking) option, provided orders of magnitude performance improvement to fulfill MediaTek’s challenging timing constraint closure requirements . Additionally, TEC provides capabilities beyond available features in the market place for a very comprehensive comparison of multiple constraints files against multiple designs at various layers of hierarchy.
The importance of equivalence checking is often limited to Top2Block equivalency as widely defined in the industry. Other important aspects of equivalency checks are often ignored as designers have not had any option to compare designs against a constraints file or multiple constraints files against one or more designs. Excellicon’s TEC (Timing Equivalence Checking is essential when performing any kind of hierarchical promotion or demotion ensuring proper propagation and correctness of all defined constraints. Additionally, when dealing with derivative designs and redo’s, the constraints issues can cause significant delay and headache for designers which leads to a widely ignored aspect of Equivalence checking, and ability to compare different versions of design to one constraints file (2D1S), or a multiple constraints file against a single design (2D1S), or even multiple constraints file against different constraints files (2D2S). Designers are also able to compare gate level design against the RTL version of the design with a given constraints file, in addition to other variations.Timing Equivalence Checks (TEC) essentially closes a gap on the timing front, which has been covered on the functional side by functional equivalency tools; LEC.
Essentially by avoiding bugs early on through complete verification of timing constraints in addition to using TEC, designers are less burdened with late-stage bug hunting which often results from inconsistencies between various versions of timing constraints files analyzed manually or through design reviews using inadequate techniques and tools. The fact that designers can start creating and validating constraints at very stages of design allows for shorter design cycles and more confidence specially during timing closure process.
“When collaborating with MediaTek’s design team, it was clear to us that tool performance was essential to their timely and accurate analysis of very large design sizes and associated timing constraints files for their designs. Having the flexibility with our unique product architecture and taking advantage of hyper-graph technology, we were able to address their performance requirements without sacrificing tool capabilities, or capacity in order to improve not only the run time but also QoR”, Said Peter Petrov CTO of Excellicon.
About Excellicon
Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Early design planning and debugging solutions automating constraints, authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Additionally, Excellicon products are targeting early design planning and viability analysis helping to detect design implementation issues very early on. Excellicon products are Constraints Manager (ConMan), Constraints Certifier (ConCert), Exception-ToolBox (ET), Budgeting-Tool Box (BT), Equivalence-Checker (TEC), ConStruct, ConTree, and ConTour address the needs of designers at every stage of SOC design and implementation in a unified environment. – Design & Timing Closure; Done Once! Done Right!
For further information contact:
Rick Eram
www.excellicon.com