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Today design teams spend many man months on defining, refining, and maintaining timing constraints. Unfortunately it is hard to quantify the exact amount of time spent on constraints definition and refinement as the process is fragmented and spread throughout the design cycle. Constraints development process is for the most part unquantified for many managers, despite the fact that majority of engineers are aware of the challenges faced every day.

Due to design schedule pressure many tape-outs results in re-spin despite all the care and effort spent in verification. Once issues are analyzed and understood, constraints are often the root cause of re-spin.

Management and designers can equally trace the timing issues to quality and consistency of constraints files and ultimately cost and lost opportunity. Many tedious hours are spent throughout various stages of design, going through constraints files trying to capture timing requirements while spending precious development time at a very high cost on SDC debug. The reason is usually because traditional and manual constraints generation and management contribute to delays and inaccuracies hard to trace and often manifest itself as distributed time syncs throughout the entire design cycle.

Here are some typical issues faced everyday by ASIC designers and the impact of it on schedules and the overall project cost based on average Man Months ( the numbers are based on a customer feedback on 10 Million gate design with 200+ clocks with some overlaps).


Automating constraints generation and management using ConMan can contribute up to 5-10 man months of saved effort for a typical SOC design cycle. This translates into less verification time, easier placement and routing of the design as well as faster turnaround time.

ConMan; our first product, is going to streamline the RTL generation and management process. Based on expert experience here are some of the key features of the tool and the impact of it on the design flow (we can certainly discuss and back up these claims in a short meeting).

ConMan's patented methods provide a unique visualization experience to the users that not only are helpful for debugging purposes, but also are used for design reviews and for exchanging information between the design teams.

  • Built-in SDC Simulator simplifies the comprehension of overall timing pictures
  • Transparent, Mode and Clock Tree browser – Visualize the entire clocking structure in a simple yet descriptive manner
  • Complete visibility inside 3rd party unknown IP's
  • Intuitive and cross linked messaging System – All information are cross linked and cross probed
  • Coverage analysis per mode for full chip or any chosen block

ConMan is the industry's first EDA tool that seamlessly eliminates the disconnect between the front-end and back-end in terms of timing assumed in test benches used for RTL simulation versus the timing coded in the SDC file for backend implementation.

  • Links RTL simulation world to the backend implementation world seamlessly at any part of the design flow
  • ConMan assembles the information coming from multiple sources and propagates the timing throughout the design
  • Any discrepancy between the RTL structure and other sources is highlighted for resolution
  • Zero impact on simulation run-times

With today's design complexity, multiple modes and shrinking geometries, the numbers of SDC files are multiplying. ConMan provides an easy method to manage all timing data in one single database, while still allowing independence to the design teams that is inherently needed during any given project. ConMan also provides a mechanism for IP teams to manage the timing data in one single repository to be reused across the organization.

  • Single database encapsulating all constraints
  • Ease of handoff through incremental database
  • Simplicity in constraints management
  • Provides mechanism to generate timing constraints to support evolving design, until maturity and finally to sign-off stage
  • Seamless flow, that allows for design teams to work independently on their respective designs with final merging of their data at the full-chip level during integration.
  • Full support for creation and management of custom IP timings and reuse in other projects