Problem We Solve
Development of the timing constraints involve intricate knowledge of functional behavior of the design as well as associated timing protocols. On one hand the front-end system architects/RTL design engineers have deep understanding of the functional and timing issues. Conversely, the effective use of timing constraints to optimally drive the downstream tool chain is well understood by the back-end engineers. Conventionally, the knowledge transfer between the front-end and back-end engineers occurs through various means such as spreadsheets or design specification documents. Such information is subsequently converted into timing constraints either manually or through somewhat automated means using internally developed scripts. Invariably, the timing intent is often lost during this process which may result in unnecessary timing closure iterations or worse, eventual timing bugs in silicon.
With shrinking geometries, increased features and fabrication costs, today's SoC's are designed to serve diverse target markets. It is a common practice to design the SoC in such a way that the die remains the same and the market differentiation occurs through package bonding options. Consequently, the different modes of operation on the same die usually result in separate timing specifications for each mode, which in turn translates into a multitude of timing constraints files, each one representing a single mode of operation. Development and management of such large amount of timing data is not only laborious and inefficient, but also extremely error prone.
Broadly, a SoC comprises of two major categories:
- Functionality - The test cases cover this (SoC Verification)
- Timing - The timing constraints covers this (Timing Closure)
SoC Verification problems have largely been solved with the availability of several tools/hardware/languages etc. Contrarily, the timing closure problems have remained the same if not actually increased. Most of these issues stem from incorrect or incomplete timing constraints, because today, the timing constraints development is still a manual process. Also, with growing complexity, hundreds of clocks, modes, and shrinking geometries, the effort spent in developing the timing constraints is simply daunting. Compounding the problem is the separation of timing constraints development, to the verification of functionality of the SoC. Front-end designers do not understand the SDC commands, whilst the back-end engineers do not understand the functionality of the SoC. Invariably, due to this separation, designers either have to run time consuming gate level simulations and/or simply rely on error prone design reviews.
Excellicon’s products have taken the formal technology to the next level and applied it towards solving the complex issues associated with the entire spectrum of timing closure. Our solutions enable complete alignment of the front-end logic simulation world to the back-end implementation world from the beginning of the chip development cycle all the way to final tape-out.
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