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Excellicon Introduces Smart Budgeting Platform, Helping with Improved Chip Performance, Power, and Area
June 2, 2016
Excellicon Inc. an innovative provider of end-to-end timing constraints and clock analysis products announced the release of its latest Smart Budgeting platform as part of its ConCert product. The Smart timing budgeting platform extends the already user-friendly budgeting capability of ConCert. The smart budgeting allows users to not only do the traditional top-down percentage based budgeting but also help the budgets to be fully analyzed in the context of Static Timing Analysis. Employing 4 unique analysis methods empowers designers to fully analyze timing budgets and squeeze every possible timing opportunity from the design. The Smart Budgeting will then be able to provide detailed ECO reports for the designer and help in redistribution of right timing budgets.
Currently, there is no feedback from the top-level design when budgeting for timing. As a result the timing budgets are traded off between various partitions without the necessary context of the top-level timing. The disconnect results in many long iterations loops between implementation and front-end design teams; in many cases leaving valuable timing budgets less than optimized leading to area, power and performance waste. Traditionally the budgeting is done early on with little feedback on the impact of such exercise as the project progresses and the floor plans are prepared and routed. Being able to get the proper feedback at all stages of the design allows the user to continually make necessary adjustments for best results.
“Doing blind budgeting will leave a lot of timing slack on the table. When the budgets are not properly optimized the result is worse chip metrics such as area, power, and performance. Using Excellicon’s methods ensures that the designer fully understands the timing tradeoffs made for each partition and not steal budgets from one partition to fix timing problem of another. Using Smart Budgeting platform will allow optimization of chip metrics which lead to better results as well as faster timing closure cycles” said Himanshu Bhatnagar, Excellicon’s CEO.
Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products ConstraintsManager, ConstraintsCerTifier, Exception ToolBox (ET), and ConDor address the needs of designers at every stage of SOC design and implementation in a unified environment. – Timing Closure; Done Once! Done Right!
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