News and Events
Excellicon’s comprehensive timing constraints solution results in continued business growth for 2017 fiscal year
June 1st, 2017
Laguna Hills, CA.
Excellicon Inc., today announced it achieved over 250% business growth expanding its install base, and customer count for fiscal year ending April 30, 2017. The revenues also grew in high double digits as a result of rapid adoption of Excellicon’s products. Continued rapid growth is driven by the need for automation of timing constraints flows and the fact that Excellicon is the only company providing a comprehensive end-to-end timing constraints and clock analysis solutions for SOC design in the market, capable of fully automating tasks such as promotion and demotion.
Exponential growth of SOC cell count along with higher integration level made possible through modern geometries is driving the need for more automation and accuracy of timing constraints for implementation of the designs on silicon. Each new geometry node adds a significant overhead for designers in terms of verification and proper implementation of their designs specifically timing constraints. New process corners, as well as process variations considerations necessitate the need for most accurate timing constraints and a large volume of data. Traditional manual timing constraints generation and manipulation is posing a risk to timing closure flow delaying product delivery, while at the same time verification of such timing constraints files are becoming increasingly complex if not impossible increasing the risk of chip failure. Manual design reviews are no longer viable or sufficient to catch issues, which always result in a long iteration loop from design implementation stage back to early RTL design stage. Traditional tools fall very short of designer needs for generation and validation of timing constraints. Designers are often forced to do many manual steps promoting, demoting or even creating multiple modes and merged modes for timing constraints.
“Need to address issues regarding the complexity of the timing constraints required for today’s chip design is driving the need for solutions which address all aspects of timing constraints development. Both front-end and back-end engineers who often get caught up in iterative loops can benefit from a unified and repeatable methodology. Designers desire to be enabled to systematically develop and verify timing constraints including complex budgeting requirements, promotion and demotion of timing constraints, and validation of complex timing intent exception is the drive behind the automation of such methodologies.” says Rick Eram VP of Sales and Marketing at Excellicon.
Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products ConstraintsManager, ConstraintsCerTifier, Exception ToolBox (ET), and ConDor address the needs of designers at every stage of SOC design and implementation in a unified environment. – Timing Closure; Done Once! Done Right!
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