ConTree

Clock Tree Analysis and Verification Platform

ConTree is a Clock Tree analysis and verification tool. It is used for both pre-CTS clocking analysis as well as post-CTS clock tree verification.


The clock tree design is one of the most critical tasks in the ASIC design. Not only it directly affects the overall timing but also has an impact on significant amount of the chip power.

The clock tree insertion is done during the P&R process, however the focus of the CTS engine is to minimize local and global skews and not so much the other aspects of the Clock tree design. Because of this, designers usually run several iterations of the clock tree synthesis, add additional information such as clock tree exceptions, creating skew groups etc., before finalizing the optimal one that meets their requirements.

Through ConTree, all such information that is needed to synthesize an ideal clock tree is automatically generated by the tool. Designers can analyze the clocking logic and generate all necessary information to drive the CTS engine to perform and ideal clock tree insertion. For pre-inserted clock trees, the tool is used to verify the correctness of clock trees for any errors. The result is improved timing, significant reduction in power and zero iterations.

The ConTree product provides the following features:

  1. Clock Tree Analysis
  2. Clock Tree Verification

Clock Tree Analysis

ConTree enables designers to explore the clocking logic for downstream interactions that is useful in determining the clock interactions, clock tree exceptions, skew groups, mode conflicts and other such information. This information is the basis of the CTS spec file which is used as the seed input to the CTS engine of the P&R tool.

Clock Tree Verification

For pre-inserted clock trees, the ConTree is used to validate the structure of the clock tree structure. The tool uses formal and other technologies to report things like redundant clocks, incorrect use of clock tree cells, Redundant logic in clock logic, crossings between voltage domains etc.

CTS verification usually results in optimized clock tree with better clock latency, skew along with overall timing. It also helps in reduced iterations


ConTree ruses the same familiar displaying of the clocking diagram as that of other products. The clock network is displayed in an intuitive and abstract manner such that the logic complexity is captured and represented as a single nodes itself. The nodes can subsequently be expanded to display leaf cells.

Through the use of the clocking diagram, users can very easily understand the clock interactions and their behavior. In addition, through ConTree, extensive reporting is enabled to probe, debug and to report the clock tree domains.