Excellicon Product Portfolio - ConCert-Exceptions Toolbox

  • Exceptions Toolbox Description
  • Structural Exceptions
  • Timing Intent Exceptions
 

ConCert-ET; Timing Constraints files often contain a great deal of exceptions. Such Exceptions are typically categorized into Structural and Timing Intent Exceptions. Most of the structural exceptions can be validated with well established formal techniques. Roughly 20% of exceptions in a typical timing constraints file are of the structural type. The challenge however lies in the remaining 80% of exceptoins which are of the timing intent nature as defined by the RTL designer at the time of functional design. Traditionally such exceptions have been defined manually and validated by manual review of constraints files.

 

Combined with ConCert solution the designer can effctively cut down on the verification of timing requirements by validating any constraints and exceptions.

Key feature highlights:

  • Comprehensive exception analysis engines for false and multi-cycle paths
  •   
  • Formal validation of structural exceptions
  • Use of SVA's generated assertions by Excellicon algorithms for validation of timing intent exceptions    
  • Structural False and Multi-Cycle paths can be validated through formal techniques
  • Generate formal proof
  • Generate independant SVA's for simulation

 

 
  • Validate Timing Intent False and Multicycle paths automatically
  • Based on Excellicon's SGEN technique analyzing Timing Intent Exceptions using several techniques
  • Eliminate chip failures due to wrong Timing Intent Exceptions
  • Automate the validation of all timing intent Exceptions

 

 

 
  • Synchronous or Asynchronous and reasons with comprehensive diagnosis
  • Inter clocks Signal Integrity checks
  • Clock relations coupled with datapath CDC analysis
  • Inter clock exceptions
  • Built-in visualization useful for cross-probing and debug analysis

 

 
  • Missing, incorrect or incomplete input and output delays
  • Correct related clocks for each IO
  • Incorrect timing delays for IO’s
  • Source synchronous interfaces
  • Checks for combinational feedthrough paths

 

 
  • Formal False path verification
  • Formal Multi-cycle path verification
  • Exception overlap & conflict analysis

 

 
  • Unconstrained paths
  • Unclassified paths
  • Quasi stable paths
  • Comprehensive diagnosis and reasoning behind unconstrained paths

 

 

Integration with tools in a typical design flow

  • Integrated solution for generation, validation, and management
  • Ease of use trough interface integration with Verdi for viewing of your design in familiar environment
  • Interface to ConCert product for one to one constrinats validation from ConMan environment
  • Ability to generate downstream tool setup files