Excellicon Product Portfolio - ConCert

  • ConCert Description
  • Constraints Coverage
  • Clock Tree
  • Clock Relations Verification
  • IO Analysis & Validation
  • Datapath Exceptions
  • Datapath Analysis
  • Constraints Equivalency
  • Timing Map Visualizer
  • IO Sim
 

ConCert; Constraints Certify is a sign-off solution providing a unique system for validation of the design timing
constraints at any stage of the ASIC flow.


ConCert uses formal algorithms to verify the timing constraints thus providing accurate in-depth analysis of both the design and its associated timing constraints.
ConCert's approach to constraints verification is different than the traditional tools available in the market today.

Traditional tools are primarily SDC linters focusing on syntax and basic correctness through the use of thousands of rules. This invariably produces a lot of noise in the output reports. Furthermore the timing intent is lost and cannot be analyzed by such traditional tools.


ConCert however makes use of its patented formal engine to analyze the behavior of the design and the SDC file. The timing intent of the design and the associated SDC file is extracted and compared to produce precise analysis reports. This method leads to elimination of noisy outputs and expands the constraints verification arena into the next generation, well beyond syntax and basic checks.


ConCert is offered stand alone or as part of ConMan platform.

Key feature highlights:

  • Full chip SDC verification using structural and formal methods
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  • Clock tree design aids
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  • In-built Clock Domain Crossing (CDC) engine
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  • Complete cross probing capability
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  • Design review reports
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  • Full TCL support
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  • Productive & rapid debugging through GUI or Shell mode of operation
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  • Supports both RTL & Gates and all HDL languages
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  • GUI and Shell
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  • Comprehensive Coverage Analysis for each mode, or for all modes
  • Clock Coverage (primary & generated)
  • IO coverage
  • Endpoints coverage (positive & negative)
  • Unconstrained paths
  • Where and why the coverage is affected

 

 
  • Comprehensive Coverage Analysis for each mode, or for all modes
  • Find missing, constant, blocked, incorrect, incompletely specified clocks etc.
  • Cross probing between the SDC, clock viewer and the messages to help pin point the issue
  • Clock reconvergences including phase reconvergent clocks
  • Full justification reports

 

 
  • Synchronous or Asynchronous and reasons with comprehensive diagnosis
  • Inter clocks Signal Integrity checks
  • Clock relations coupled with datapath CDC analysis
  • Harmonic and non-harmonic checking
  • Inter clock exceptions
  • Case analysis conflicts
  • Logical vs. physically exclusive validation
  • Built-in visualization useful for cross-probing and debug analysis

 

 
  • Missing, incorrect or incomplete input and output delays
  • Correct related clocks for each IO
  • Incorrect timing delays for IO’s
  • Find unconstrained IO's
  • Source synchronous interfaces
  • Checks for combinational feedthrough paths

 

 
  • Formal False path verification
  • Formal Multi-cycle path verification
  • Exception overlap & conflict analysis

 

 

  • Unconstrained paths
  • Unclassified paths
  • Quasi stable paths
  • Comprehensive diagnosis and reasoning behind unconstrained paths

 

 
  • Compare any number of constraints files
  • Validate the differences between constraints files
  • Top level against lower level SDC validation

 

Timing map is an innovative mean of visualizing timing arcs for easy debug and analysis.

Timing map overlays constrints over design structure empowering user to visulaize the issues in constraints files.

  • Inspect the entire constraints file in one easy to understand timing map
  • Visualize timing arcs and associated relations with ease
  • Quickly pinpoint missing constraints
  • Fast identificaiton of incorrect constraints

 

 
  • Visulaize the IO behavior
  • Inspect clock relations in a single signal viewer